Content addressable memory match line sensing techniques

ABSTRACT

A content addressable memory ( 10 ) comprising a group of content addressable cells ( 20 ) and a group of corresponding match switches ( 30 ) coupled by a first match line ( 36 ) that is switched to a first voltage in the event all of the match switches in the group are in a first state and is switched to a second range of voltages in the event one or more of the match switches in the group are in a second state. Apparatus for detecting the state of the first match line comprises a second line ( 56 ), a second transistor ( 58 ) coupled to the second line and arranged to place a third voltage on the second line that is different from the first voltage and the second range of voltages and a differential amplifier ( 70 ) arranged to detect the difference in voltage between the first match line and the second line.

BACKGROUND OF THE INVENTION

[0001] This invention relates to memory cells and more particularlyrelates to content addressable memory cells.

[0002] Many memory devices store and retrieve data by addressingspecific memory locations. As a result, this path often becomes thelimiting factor for systems that rely on fast memory access. The timerequired to find an item stored in memory can be reduced considerably ifthe stored data item can be identified for access by the content of thedata itself rather than by its address. Memory that is accessed in thisway is called content-addressable memory (CAM). CAM provides aperformance advantage over other memory search algorithms (such asbinary and tree-based searches or look-aside tag buffers) by comparingthe desired information against the stored data simultaneously, oftenresulting in an order-of-magnitude reduction of search time.

[0003] A CAM typically has two sets of sense amplifiers, amplifiers forread data sensing and for match line signal sensing. Referring to FIG.1, a CAM 10 includes a row 20 of CAM cells, including CAM cells 22-24.

[0004] Each of cells 22-24 is connected through bit lines, such as lines38-39, to a read sense circuit, such as circuit 26. Circuit 26 comprisesa differential amplifier that receives input from lines 38-39.

[0005] Cells 22-24 are connected to a group 30 of corresponding matchswitches 32-34 that are connected to a match line 36. Each of matchswitches 32-34 is switchable to a first state in the event of a matchbetween data stored in a corresponding cell and test data introduced onbit lines and is switchable to a second state in the event of a mismatchbetween data in the corresponding cell and the test data on the bitlines.

[0006] Match line 36 is coupled to a match sense circuit 40. Rather thanusing a differential amplifier as found in read sense circuit 26, aconventional match sense circuit employs an asymmetric circuit, such astransistors 41-42, which are not identical. Another transistor 43 isconnected between transistors 41-42 and ground potential as shown. Asupply voltage is used as a reference voltage applied to terminal 44. Inorder to sense the voltage state of line 36, the circuit senses theasymmetric ratio of the reference voltage and the voltage on line 36.The differential sensed margin must remain relatively high forvariations of power supply, temperature, wafer process variation, andthe influences of skew lots. This requirement reduces the margin ofaccuracy for the circuit, reduces the speed at which the voltage stateof line 36 can be sensed, and requires laborious and increased designtime for each different technology used to implement the CAM. Thisinvention addresses these problem and provides a solution.

[0007] Further limitations and disadvantages of conventional andtraditional approaches will become apparent to one of skill in the art,through comparison of such systems with the present invention as setforth in the remainder of the present application with reference to thedrawings.

BRIEF SUMMARY OF THE INVENTION

[0008] One apparatus embodiment of the invention is useful in a contentaddressable memory comprising a group of content addressable cells and agroup of corresponding match switches coupled by a first match line.Each match switch is switchable to a first state in the event of a matchbetween data stored in a corresponding cell and test data and isswitchable to a second state in the event of a mismatch between data inthe corresponding cell and the test data. The first match line isswitched to a first voltage in the event all of the match switches inthe group are in the first state and is switched to a second range ofvoltages in the event one or more of the match switches in the group arein the second state. In such an environment, the state of the firstmatch line is detected by apparatus comprising a second line and asecond gate outside the group of corresponding match switches coupled tothe second line and arranged to place a third voltage on the secondline. The third voltage is different from the first voltage and thesecond range of voltages. A differential amplifier is coupled to thefirst match line and the second line and is arranged to detect thedifference in voltage between the first match line and the second line.

[0009] One method embodiment of the invention is useful in a contentaddressable memory comprising a group of content addressable cells and agroup of corresponding match switches coupled by a first match line.Each match switch is switchable to a first state in the event of a matchbetween data stored in a corresponding cell and test data and isswitchable to a second state in the event of a mismatch between data inthe corresponding cell and the test data. The first match line isswitched to a first voltage in the event all of the match switches inthe group are in the first state and is switched to a second range ofvoltages in the event one or more of the match switches in the group arein the second state. In such an environment, a the state of the firstmatch line is detected by a method comprising placing a second line inthe environment of the first match line and placing a third voltage onthe second line. The third voltage is different from the first voltageand the second range of voltages. The difference in voltage between thefirst match line and the second line is detected.

[0010] By using the foregoing techniques, the state of a match line canbe detected with a degree of accuracy and reliability previousunattained.

[0011] These and other advantages and novel features of the presentinvention, as well as details of an illustrated embodiment thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a schematic diagram of a prior art match line detectioncircuit in an exemplary content addressable cell.

[0013]FIG. 2 is a schematic diagram of a first form of contentaddressable cell made in accordance with the invention.

[0014]FIG. 3 is a schematic diagram of a second form of the cell shownin FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

[0015] Referring to FIG. 2, one form of CAM 50 made in accordance withthe invention includes the same type of CAM cells 22-24, match switches32-34 and match line 36 shown in FIG. 1. More specifically, matchswitches 32-36 comprise n-channel transistors having a narrow range ofphysical sizes. In practice, transistors 32-34 are made substantiallyidentical in size.

[0016] Another line 56 is located in the same environment as line 36 andhas the same loading as line 36. More specifically, the diffusionloading on both lines 36 and 56 is substantially identical. P-channeltransistors 37 and 57 are used to precharge lines 36 and 56,respectively, to VDD. Precharge transistor 57 is identical to prechargetransistor 37.

[0017] Line 56 is connected to an n-channel switching transistor 58.More specifically, transistor 58 has a drain 60 connected to line 56, asource 62 connected to ground potential and a gate 64 connected to avoltage supply VDD. Transistor 58 is one half the physical size ofswitches 32-34. Line 56 provides a differential signal for line 36.

[0018] Due to the connection to VDD, transistor 58 is turned on anddrives line 56, for example, about 100 millivolts below VDD. When eachof transistors 32-34 is turned off, line 36 already is precharged to avoltage near VDD and above the voltage of line 56. When one oftransistors 32-34 is turned on, the voltage of line 36 is driven downbelow the voltage of line 56. When additional transistors in group 30(e.g., transistors 32-34) are turned on, the voltage of line 36 isdriven further below the voltage present when only one of transistors32-34 is turned on. Depending on the number of transistors 32-34 turnedon, a range of voltages below the voltage on line 56 is provided. Forall of the foregoing conditions, the voltage on line 56 provides areliable differential signal for the voltage on line 36.

[0019] A differential sense amplifier 70 detects the difference involtage between line 36 and line 56. In FIG. 2, the differential inputtransistors are 72 and 74. The gates of transistors 72 and 74 areconnected to lines 36 and 56, respectively. Another transistor 75 isconnected to ground potential as shown.

[0020] A sense load 80 is connected to transistors 72 and 74 as shown.

[0021] Referring to FIG. 3, a single line 56 can provide a referencesignal for several rows of CAM cells. More specifically, cell row 20 isidentical to the cell row shown in FIG. 2. A cell row 20A comprises CAMcells 22A-24A and corresponding match switches 32A-34A connected asshown to a match line 36A. A cell row 20B comprises CAM cells 22B-24Band corresponding match switches 32B-34B connected as shown to a matchline 36B. Differential amplifiers 70, 70A and 70B comprising transistorpairs 72 and 74, 72A and 74A, and 72B and 74B and additional transistors75, 75A and 75B are connected as shown. Line 56 is connected to thegates of each of transistors 74, 74A and 74B as shown. Sense loads 80,80A and 80B are connected as shown.

[0022] While the invention has been described with reference to one ormore preferred embodiments, those skilled in the art will understandthat changes may be made and equivalents may be substituted withoutdeparting from the scope of the invention. In addition, manymodifications may be made to adapt a particular step, structure, ormaterial to the teachings of the invention without departing from itsscope. Therefore, it is intended that the invention not be limited tothe particular embodiment disclosed, but that the invention will includeall embodiments falling within the scope of the appended claims.

What is claimed is:
 1. In a content addressable memory comprising agroup of content addressable cells and a group of corresponding matchswitches coupled by a first match line, each match switch beingswitchable to a first state in the event of a match between data storedin a corresponding cell and test data and being switchable to a secondstate in the event of a mismatch between data in the corresponding celland the test data, the first match line being switched to a firstvoltage in the event all of the match switches in the group are in thefirst state and being switched to a second range of voltages in theevent one or more of the match switches in the group are in the secondstate, apparatus for detecting the state of the first match linecomprising: a second line; a second switch outside the group ofcorresponding match switches coupled to the second line and arranged toplace a third voltage on the second line, the third voltage beingdifferent from the first voltage and the second range of voltages; and adifferential amplifier coupled to the first match line and the secondline arranged to detect the difference in voltage between the firstmatch line and the second line.
 2. The apparatus of claim 1 wherein thematch switches in the group comprise a predetermined first size rangeand wherein the second switch comprises a second predetermined size lessthan the first predetermined size range.
 3. The apparatus of claim 2wherein the match switches in the group comprise substantially the samesize so that the first size range comprises a first predetermined sizeand wherein the second predetermined size is substantially one half thefirst predetermined size.
 4. The apparatus of claim 1 wherein the matchswitches comprise transistors.
 5. The apparatus of claim 4 wherein thesecond switch comprises a transistor.
 6. The apparatus of claim 1wherein the third voltage lies between the first voltage and the secondrange of voltages.
 7. The apparatus of claim 1 and further comprising asense amplifier coupled to the differential amplifier.
 8. The apparatusof claim 1 and further comprising: a second group of content addressablecells and a second group of corresponding match switches coupled by athird match line, each match switch in the second group being switchableto a first state in the event of a match between data stored in acorresponding cell and test data and being switchable to a second statein the event of a mismatch between data in the corresponding cell andthe test data, the third match line being switched to the first voltagein the event all of the match switches in the second group are in thefirst state and being switched to the second range of voltages in theevent one or more of the match switches in the second group are in thesecond state; and a second differential amplifier coupled to the thirdmatch line and the second line arranged to detect the difference involtage between the third match line and the second line.
 9. Theapparatus of claim 1 wherein the second line has the same loading as thefirst match line.
 10. The apparatus of claim 1 wherein the second lineis subject to the same environment as the first match line.
 11. In acontent addressable memory comprising a group of content addressablecells and a group of corresponding match switches coupled by a firstmatch line, each match switch being switchable to a first state in theevent of a match between data stored in a corresponding cell and testdata and being switchable to a second state in the event of a mismatchbetween data in the corresponding cell and the test data, the firstmatch line being switched to a first voltage in the event all of thematch switches in the group are in the first state and being switched toa second range of voltages in the event one or more of the matchswitches in the group are in the second state, a method of detecting thestate of the first match line comprising: placing a second line in theenvironment of the first match line; placing a third voltage on thesecond line, the third voltage being different from the first voltageand the second range of voltages; and detecting the difference involtage between the first match line and the second line.
 12. The methodof claim 11 wherein the third voltage lies between the first voltage andthe second range of voltages.
 13. The method of claim 11 wherein thecontent addressable memory further comprises a second group of contentaddressable cells and a second group of corresponding match switchescoupled by a third match line, each match switch in the second groupbeing switchable to a first state in the event of a match between datastored in a corresponding cell and test data and being switchable to asecond state in the event of a mismatch between data in thecorresponding cell and the test data, the third match line beingswitched to the first voltage in the event all of the match switches inthe second group are in the first state and being switched to the secondrange of voltages in the event one or more of the match switches in thesecond group are in the second state and wherein the method furthercomprises detecting the difference in voltage between the third matchline and the second line.
 14. The method of claim 11 and furthercomprising loading the second line substantially the same as the firstmatch line.
 15. The method of claim 11 and further comprising subjectingthe second line to substantially the same environment as the first matchline.